For many years it has been postulated that ferroelectric materials, i.e., materials that exhibit characteristics similar to ferro magnetic materials, would be competitive with magnetic core and semiconductor memories. This has been suggested in an article "Ferroelectric Arrays: Competition For Core and Semiconductor Memories", beginning on page 30 of Digitial Design in the June 1973 issue. Ferroelectric materials, however, have not become commercially successful for use in semiconductors for a variety of reasons, principally because a good quality thin film could not be applied to a substrate and fabricated into circuits.
A recent development, which shows some promise as a ferroelectric material, is the PLZT family, which is an abbreviation for a ceramic oxide composition containing lead, lanthanum, titanium and zirconium. The phrase "PLZT family" as used herein refers to various compositions of PLZT or combinations of two or more of the components, such as PZT (no lanthanum present), PLT (no zirconium present) PZ (no lanthanum or titanium present) and PT (no lanthanum or zirconium present). While the theoretical suitability of PLZT family materials as memory elements has been known for some time, practical applications of the material in the form of a thin film on a silicon wafer or other substrates has evaded the art. The formation of such a suitable thin PLZT film is the subject of a copending application Ser. No. 057,323 filed concurrently herewith. Although that application describes a suitable process for deposition of the thin PLZT film, it was found that conventional etching procedures, as used in the manufacture of semiconductor integrated circuits, cannot produce a patterned PLZT which is successful as an element of an integrated circuit.
Prior attempts at a wet process etching for PLZT family materials were disclosed in relation to large blocks or layers of material. There has not been a wet etching process suitable for etching PLZT family films which allowed for production of a well defined pattern of the size suitable for MOS applications. Typically, the film patterns are less than 2000 square microns in size and tolerances for various leads are generally one micron or less, thus the etching process must be controllable. Limited work has been done to pattern PLZT family thin films using reactive ion etching (RIE). However, RIE patterning requires complex and expensive equipment. The added expense of RIE processing can make the economical production of integrated circuits impossible. Prior wet process etching attempts to pattern PLZT family materials were not suitable for producing a well defined pattern with the required electronic or photosensitive properties.
The present invention provides an economical, simple and effective wet etching process for patterning PLZT family thin films. This allows the PLZT family of materials to be economically utilized in microcircuit technology.